In general, the design of a full-adder is usually simplified by a Karnaugh map, and the simplified result is applied directly to the design of full-adders. However, the voltage of output signals of a circuit will be lost, if the transistor count of such design drops to a minimum of 10 transistors (10T). Particularly, the loss occurred in an application of a serially connected multi-bit adders becomes very important, because the signals may have to be transmitted from the lowest bit to the highest bit in the worst scenario of a serial connection. Therefore, a lower signal driving capability will significantly affect the overall performance of the speed of the whole circuit and consume more power.
A loss of output potential generally occurs at a circuit structure for lowering its transistor count, and a pass transistor logic is used to implement the circuit structure, and thus there will be a loss of potential of an output voltage under certain specific conditions, and this problem is known as a “threshold loss” problem. In a negative-channel metal oxide semiconductor (NMOS), a high signal is transmitted when the NMOS transistor is turned on, and the voltage (Vdd−Vtn) of its output signal will be lost by one Vtn, wherein Vtn is a NMOS-threshold voltage (typically having a value of 0.6˜0.8V for the 0.35 um process, if the cost-effectiveness of the substrate is taken into account). In other words, the electric potential of the output is not equal to the operating voltage, but it has a voltage equal to one Vtn smaller than the operating voltage. The same problem occurs in a positive-channel metal oxide semiconductor (PMOS), and if the PMOS transmits a low electric potential, the voltage of the output signal will be one Vtp greater than the electric potential, wherein Vtp is the PMOS-threshold voltage (which typically has a value of −0.7˜−0.95V, if the cost-effectiveness of the substrate is taken into account for the 0.35 um process). In other words, the outputted electric potential is not equal to the operating voltage, but the voltage is one Vtp greater than the operating voltage. To solve this problem, an inverter is usually added to the circuit structure to provide a complementary control signal. In the meantime, a PMOS and an NMOS are used for transmitting signals and they are known as transmission gates as described in [A. Shams and M. Báyoumi, “A Novel High-Performance COMS 1-Bit Full-Adder Cell” IEEE Trans. Circuits and Systems-II, Vol. 47 No. 5, May 2000.] [N. Zhuang and H. Wu, “A New design of the CMOS full-adder,” IEEE J. of Solid state circuits, Vol. 27, No. 5, pp. 840-844, May 1992.]. However, all of these also cause an overall increase of the transistor count and the silicon area and increase the power consumption.
If a circuit structure uses a MOS as a switch component and such switch is used for a serial connection, there will be a signal transmission delay, and the speed of the signal transmission and the number of levels (N) of the serial connection have a loss proportional to the number of levels in square (N2) provided that the serially connected switches have not used a buffer or an inverter for the division and compensation, and this phenomenon is called an “Elmore Delay”. Although the aforementioned adder having a high transistor count can overcome the threshold loss problem of the threshold voltage, yet the Elmore delay problem still exists.
However, there are more than 40 present designs of ten-transistor (10T) full-adders as disclosed by [Hung Tien Bui, Yuke Wang and Yingtao Jiang; “Design and analysis of low-power 10-transistor full-adders using novel XOR-XNOR gates” IEEE Transactions on Systems II: Express Briefs, Volume: 49, Issue: 1, pp. 25-30. January 2002] and [R. Shalem, E. John, and L. K. John, “A novel low power energy recovery full-adder cell,” in Proc. Great Lakes Symp. VLSI, pp. 380-383, 1999], and the potential of the output signal has a multi-threshold loss, in addition to the loss of two times of Vt (2Vtn+Vtp or 2Vtp+Vtn). The multi-threshold loss of the threshold voltage causes a more serious Elmore delay for driving a serial connection in a ten-transistor full-adder design, and its operating voltage cannot be lower than 2.8V (for a 0.35 um fabrication process), and thus greatly lowering the practicability of adders of this sort.
An adder composed of ten transistors (10T) definitely has advantages on its layout area, but finding a way of maintaining a high performance and a lower operating voltage in such design with a very low transistor count is facing a severe challenge. As to the static energy-recovery full-adder (SERF) having the best performance in a 10T design, the SERF circuit structure as shown in FIG. 1 is taken for example, and its formula based on the algorithm of the full-adder is Sum=(A⊙B).Cin+(A⊕B). Cin; Cout=(A⊕B).Cin+(A⊙B).A. If a primary XNOR logic block 1 inputs an addend A and a summand B and whose potentials are high (A=1, B=1), the two PMOS transistors at the top will be off, and the output Q1 of the primary XNOR logic block 1 can be obtained from the two NMOS transistors at a high potential from the bottom. Since there is a threshold loss of the voltage loss problem if the NMOS transistor transmits a high potential, therefore the maximum potential can reach up to Vdd−Vtn. This output controls a transistor gate of a logic circuit such as a secondary XNOR logic block 2 for finally producing a sum output Sum and a 2-to-1 multiplexer 3 for producing a carry output Cout. In addition, the voltage loss occurs at the secondary XNOR logic block 2 and the NMOS transistor in the 2-to-1 multiplexer 3, and the maximum potential of their carry output Cout can reach up to Vdd−2Vtn, and their minimum potential can rise up to |Vtp| due to the voltage loss of the PMOS transistor in the 2-to-1 multiplexer 3, so that the final output has a multi-threshold voltage loss problem.
The same situation may occur in other disclosed ten-transistor full-adders, and thus the operating voltage of the current 10T full-adders cannot be too low, and the operating voltage cannot be lower than 2Vtn+|Vtp| (or 2|Vtp|+Vtn), or else the full-adders cannot be used in a circuit operated at a low voltage. In addition, a general adder usually uses a plurality of bits connected in series for its application, and thus a transmission with a carry output should be taken into consideration. Under the situation of such circuit having a carry output potential with a poor driving capability, the performance of the serial connection will be not as good. In addition, such design also causes an Elmore delay in a serial connection and results in a low performance, so that the present 10T full-adders have difficulties in their applications. These two drawbacks severely affect the performance of a serial connection.
To solve the foregoing problems, some prior arts use more transistors. In other words, there will be no such problem if both PMOS and NMOS transmit signals at the same time, and this structure is called a transmission gate. For instance, if the aforementioned pass transistor logic uses one NMOS transistor, the structure of the transmission gate will require another inverter (2T) in addition to the use of MOS and PMOS, and thus the transmission gate actually has three more transistors than the pass transistor logic. In other words, the transmission gate cannot be used with the limitation often transistors (10T).
The aforementioned structure still has the Elmore delay problem when the MOS transistor is used for transmitting signals (simultaneously using one NMOS or PMOS or two MOS for the transmission), except that no loss of potential occurs in the transmission gate structure. In addition, the PMOS and the NMOS are connected in parallel while transmitting signals, and thus the resistance of an equivalent transmission is smaller, and the influence of the Elmore effect will become lesser.
In summation of the description above, the present 10T full-adder has two major problems: 1. A multi-threshold loss problem that maintains the operating voltage of a full-adder at a level which is not too low. 2. A serious Elmore delay that causes a low performance and makes the application of the present 10T full-adder very difficult.
Although the design of other full-adders having a higher transistor count can solve the foregoing problem, the design adopts 16˜28 transistors or even more and thus incurring an additional design cost as well as increasing the manufacturing cost for the additional transistors.